1.Which writing mechanism forms the backbone of the bus snooping mechanism?
a) write-back
b) write-through
c) no caching of write cycles
d) write buffer
Answer: c
Explanation: The no caching of write cycle seems to be wasteful because it does not update the cache, and if any previous data is cached, that entry might be an error and is not used. So the processor access data from the main memory but this writing scheme forms the backbone of the bus snooping system for the coherency issue.
2. What is the main idea of the writing scheme in the cache memory?
a) debugging
b) accessing data
c) bus snooping
d) write-allocate
Answer: c
Explanation: There are four main writing scheme in the cache memory which is, write-through, write-back, no caching of the write cycle and write buffer. All these writing schemes are designed for bus snooping which can reduce the coherency.
3. In which scheme does the data write via a buffer to the main memory?
a) write buffer
b) write-back
c) write-through
d) no caching of the write cycle
Answer: a
Explanation: The write-buffer is slightly similar to the write-through mechanism in which data is written to the main memory but in write buffer mechanism data writes to the main memory via a buffer.
4. . Which of the following can allocate entries in the cache for any data that is written out?
a) write-allocate cache
b) read-allocate cache
c) memory-allocate cache
d) write cache
Answer: a
Explanation: A write-allocate cache allocates the entries in the cache for any data that is written out. If the data is transferred to the external memory so that, when it is accessed again, the data is already waiting in the cache. It works efficiently if the size of the cache is large and it does not overwrite even though it is advantageous.
5. Which of the following uses a bus snooping mechanism?
a) MC88100
b) 8086
c) 8051
d) 80286
Answer: a
Explanation: The bus snooping mechanism uses a combination of cache tag status, write policies and bus monitoring to ensure coherency. MC88100 or MC88200 uses bus snooping mechanism.
6. What leads to the development of MESI and MEI protocol?
a) cache size
b) cache coherency
c) bus snooping
d) number of caches
Answer: b
Explanation: The problem of cache coherency lead to the formation of two standard mechanisms called MESI and MEI protocol. MC88100 have MESI protocol and MC68040 uses an MEI protocol.
7. Which of the following is also known as Illinois protocol?
a) MESI protocol
b) MEI protocol
c) Bus snooping
d) Modified exclusive invalid
Answer: a
Explanation: The MESI protocol is also known as Illinois protocol because of its formation at the University of Illinois.
8. What does MESI stand for?
a) modified exclusive stale invalid
b) modified exclusive shared invalid
c) modified exclusive system input
d) modifies embedded shared invalid
Answer: b
Explanation: The MESI protocol supports a shared state which is a formal mechanism for controlling the cache coherency by using the bus snooping techniques. MESI refers to the states that cached data can access. In MESI protocol, multiple processors can cache shared data.
9.. What does MEI stand for?
a) modified embedded invalid
b) modified embedded input
c) modified exclusive invalid
d) modified exclusive input
Answer: c
Explanation: MEI protocol is less complex and is easy to implement. It does not allow shared state for the cache.
10. Which protocol does MPC601 use?
a) MESI protocol
b) MEI protocol
c) MOSI protocol
d) MESIF protocol
Answer: a
Explanation: MPC601 uses a MESI protocol, that is they have a shared state for data accessing in the cache. It can reduce the cache coherency but the cache coherency is processor specific. So different processors have different cache coherency implementations.
11. Which of the following allows the reuse of the software and the hardware components?
a) platform based design
b) memory design
c) peripheral design
d) input design
Answer: a
Explanation: The platform design allows the reuse of the software and the hardware components in order to cope with the increasing complexity in the design of embedded systems.
12. Which of the following is the design in which both the hardware and software are considered during the design?
a) platform based design
b) memory based design
c) software/hardware codesign
d) peripheral design
Answer: c
Explanation: The software/hardware codesign is the one which having both hardware and software design concerns. This will help in the right combination of the hardware and the software for the efficient product.
13. What does API stand for?
a) address programming interface
b) application programming interface
c) accessing peripheral through interface
d) address programming interface
Answer: b
Explanation: The platform-based design helps in the reuse of both the hardware and the software components. The application programming interface helps in extending the platform towards software applications.
14. Which activity is concerned with identifying the task at the final embedded systems?
a) high-level transformation
b) compilation
c) scheduling
d) task-level concurrency management
Answer: d
Explanation: There are many design activities associated with the platforms in the embedded system and one such is the task-level concurrency management which helps in identifying the task that needed to be present in the final embedded systems.
15. In which design activity, the loops are interchangeable?
a) compilation
b) scheduling
c) high-level transformation
d) hardware/software partitioning
Answer: c
Explanation: The high-level transformation is responsible for the high optimizing transformations, that is, the loops can be interchanged so that the accesses to array components become more local.
16. Which design activity helps in the transformation of the floating point arithmetic to fixed point arithmetic?
a) high-level transformation
b) scheduling
c) compilation
d) task-level concurrency management
Answer: a
Explanation: The high-level transformation are responsible for the high optimizing transformations, that is, for the loop interchanging and the transformation of the floating point arithmetic to the fixed point arithmetic can be done by the high-level transformation.
17. Which design activity is in charge of mapping operations to hardware?
a) scheduling
b) high-level transformation
c) hardware/software partitioning
d) compilation
Answer: c
Explanation: The hardware/software partitioning is the activity which is in charge of mapping operations to the software or to the hardware.
18.Which of the following is approximated during hardware/software partitioning, during task-level concurrency management?
a) scheduling
b) compilation
c) task-level concurrency management
d) high-level transformation
Answer: a
Explanation: The scheduling is performed in several contexts. It should be approximated with the other design activities like the compilation, hardware/software partitioning, and task-level concurrency management. The scheduling should be precise for the final code.
19. Which of the following is a process of analyzing the set of possible designs?
a) design space exploration
b) scheduling
c) compilation
d) hardware/software partitioning
Answer: a
Explanation: The design space exploration is the process of analyzing the set of designs and the design which meet the specification is selected.
20. Which of the following is a meet-in-the-middle approach?
a) peripheral based design
b) platform based design
c) memory based design
d) processor design
Answer: b
Explanation: The platform is an abstraction layer which covers many possible refinements to a lower level and is mainly follows a meet-in-the-middle approach.
21. The time taken to respond to an interrupt is known as
a) interrupt delay
b) interrupt time
c) interrupt latency
d) interrupt function
Answer: c
Explanation: The interrupts are the most important function of the embedded system and are responsible for many problems while debugging the system. The time taken to respond to an interrupt is called the interrupt latency.
22. Into how many parts does the interrupt can split the software?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: The software interrupt can split into two parts. These are foreground work and background work.
23.Which of the following allows the splitting of the software?
a) wait statement
b) ready
c) interrupt
d) acknowledgement
Answer: c
Explanation: The interrupt can make the software into two main parts and these are foreground work and background work.
24. Which part of the software is transparent to the interrupt mechanism?
a) background
b) foreground
c) both background and foreground
d) lateral ground
Answer: a
Explanation: The interrupt mechanism is transparent to the background software, that is, the background software is not aware of the existence of the foreground software.
25. Which part of the software performs tasks in response to the interrupts?
a) background
b) foreground
c) lateral ground
d) both foreground and background\
Answer: b
Explanation: In the foreground work, the tasks are performed in response to the interrupts but in the background work, the tasks are performed while waiting for an interrupt.
26.in which of the following method does the code is written in a straight sequence?
a) method 1
b) timing method
c) sequence method
d) spaghetti method
Answer: d
Explanation: In the spaghetti method, the code is written in a straight sequence in which the analysis software goes and polls the port to see if there is data.
27. . Which factor depends on the number of times of polling the port while executing the task?
a) data
b) data transfer rate
c) data size
d) number of bits
Answer: b
Explanation: The data transfer rate can determine the number of times the port is polled while executing the task.
28. Which of the following can improve the quality and the structure of a code?
a) polling
b) subroutine
c) sequential code
d) concurrent code
Answer: b
Explanation: The subroutine can improve the quality and the structure of the code. By using the polling method, as the complexity increases the software structure rapidly fall and it will become inefficient. So the subroutine method is adopted.
29.. Which of the following are asynchronous to the operation?
a) interrupts
b) software
c) DMA
d) memory
Answer: a
Explanation: The interrupts are asynchronous to the operation and therefore can be used with systems that are the event as opposed to the time driven.
30.Which of the following can be used to create time-driven systems?
a) memory
b) input
c) output
d) interrupts
Answer: d
Explanation: The interrupts which are asynchronous can be used with systems that are the event as opposed to the time driven.